1 Technical Field of the Invention
The present invention relates generally to an operational amplifier designed to have an increased output range.
2 Background Art
FIG. 4 shows an example of conventional operational amplifiers. The shown operational amplifier includes a differential amplifier 50, an output circuit 60, and a control circuit 70. The differential amplifier 50 outputs a signal as a function of a potential difference between an input signal to a non-inverting input Tp (+input) and an input signal to an inverting input Tn (xe2x88x92input). The output circuit 60 is made of the so-called push-pull circuit including a pair of output transistors Tr61 and Tr62. The control circuit 70 controls the output transistors Tr61 and Tr62 as a function of the output of the differential amplifier 50 and outputs a signal as a function the potential difference between the input signal to the non-inverting input Tp and the input signal to the inverting input Tn from an output terminal To connected to a junction of the output transistors Tr61 and Tr62 (i.e., emitters of the transistors Tr61 and Tr62).
The differential amplifier 50 includes PNP transistors Tr50 and Tr51. The PNP transistor Tr50 connects at an emitter thereof with a power supply line Lv leading to a positive voltage terminal of a dc power supply (not shown) through a power supply terminal Tv and at a base thereof with a constant-current source (not shown) through a current control terminal Tc and outputs constant currents controlled by the constant-current source from three collectors thereof. Similarly, the PNP transistor Tr51 connects at an emitter thereof with the power supply line Lv and at a base thereof with the constant-current source through the current control terminal Tc and outputs constant currents from by the constant-current source from two collectors thereof.
Each of the transistors Tr50 and Tr51 works as a constant-current source for the differential amplifier 50. Specifically, the current outputted from each of the transistors Tr50 and Tr51 activates eight transistors Tr52 to Tr59, as described later in detail, to output the signal as a function of the potential difference between the input signal to the non-inverting input Tp and the input signal to the inverting input Tn.
The transistor Tr52 is a PNP transistor which connects at a base with the non-inverting input Tp, at an emitter with the first collector of the PNP transistor Tr51 through a diode D51, and at a collector with a ground line Lg. The ground line Lg is supplied with the power from the dc power supply (not shown) along with the power supply line Lv and connects with a negative voltage terminal of the dc power supply through a ground terminal Tg. The diode D51 connects at a cathode with the emitter of the PNP transistor Tr52 and at an anode with the first collector of the PNP transistor Tr51.
The transistor Tr53 is a PNP transistor which connects at a base with a junction of the anode of the diode D51 and the first collector of the PNP transistor Tr51 and at an emitter with the first collector of the PNP transistor Tr50.
The transistor Tr54 is a PNP transistor which connects at a base with the inverting input Tn, at an emitter with the second collector of the PNP transistor Tr51 through a diode D52, and at a collector with the ground line Lg. The diode D52 connects at a cathode with the emitter of the PNP transistor Tr54 and at an anode with the second collector of the PNP transistor T51.
The transistor Tr55 is a PNP transistor which connects at a base with a junction of the anode of the diode D52 and the second collector of the PNP transistor Tr51 and at an emitter with the first collector of the PNP transistor Tr50 along with the emitter of the PNP transistor Tr53.
The transistor Tr56 is a PNP transistor which connects at an emitter with the second collector of the PNP transistor Tr50, at a base with the collector of the PNP transistor Tr53, and at a collector with the ground line Lg.
The transistor Tr57 is a PNP transistor which connects at an emitter with the third collector of the PNP transistor Tr50, at a base with the collector of the PNP transistor Tr55, and at a collector with the ground line Lg.
The transistor Tr58 is an NPN transistor which connects at a collector with the collector of the PNP transistor Tr53 and the base of the PNP transistor Tr56 at an emitter with the ground line Lg, and at a base with the collector thereof.
The transistor Tr59 is an NPN transistor which connects at a collector with the collector of the PNP transistor Tr55 and the base of the PNP transistor Tr57 at an emitter with the ground line Lg, and at a base with the base of the PNP transistor Tr58 to form a current mirror along with the NPN transistor Tr58.
The control circuit 70 also includes PNP transistors Tr70 and Tr71 and six transistors Tr72 to Tr77 activated by a supply of power from the transistors Tr70 and Tr71. The PNP transistor Tr70 connects at an emitter thereof with the power supply line Lv, and at a base thereof with the constant-current source through the current control terminal Tc and outputs constant currents from by the constant-current source from four collectors thereof. Similarly, the PNP transistor Tr71 connects at an emitter thereof with the power supply line Lv and at a base thereof with the constant-current source through the current control terminal Tc and outputs constant currents from by the constant-current source from five collectors thereof.
The transistor Tr72 is an NPN transistor which connects at a base with the emitter of the PNP transistor Tr57, at a collector with the first collector of the PNP transistor Tr70, and at an emitter with the ground line Lg through a resistor R71.
The transistor Tr73 is an NPN transistor which connects at a base with the emitter of the NPN transistor Tr72, at an emitter with the ground line Lg, and at a collector with the base of the PNP transistor Tr57 through a phase compensating capacitor C71, the bases of the output transistors Tr61 and Tr62 of the output circuit 60, and the five collectors of the PNP transistor Tr71.
The transistor Tr74 is an NPN transistor which connects at an emitter with the collector of the NPN transistor Tr72 and the first collector of the PNP transistor Tr70, and at a collector with the ground line Lg, and at a base with the second to fourth collectors of the PNP transistor Tr70.
The transistor Tr75 is an NPN transistor which connects at a collector with the base of the PNP transistor Tr74 (i.e., the second to fourth collectors of the PNP transistor Tr70), at an emitter with the ground line Lg, and at a base with a collector thereof.
The transistor Tr76 is an NPN transistor which connects at a collector with the output terminal To, at an emitter with the ground line Lg, and at a base with the base of the NPN transistor Tr75 to form a current mirror along with the NPN transistor Tr75.
The transistor Tr77 is an NPN transistor which connects at a collector with the five collectors of the PNP transistor Tr71 (i.e., the bases of the output transistors Tr61 and Tr62 of the output circuit 60 and the collector of the NPN transistor Tr76), at an emitter with the collector of the NPN transistor Tr76 (i.e., the output terminal To), at a base directly with the emitter of the output transistor Tr61 and with the emitter of the output transistor Tr62 through a resistor R61.
In the output circuit 60, the output transistor Tr61 connects at the collector with the power supply line Lv. The output transistor Tr62 connects at the collector with the ground line Lg and at the emitter with the emitter of the output transistor Tr61 through the resistor R61 and with the output terminal To.
In operation, when the differential amplifier 50 receives the input signals to the non-inverting input Tp and the inverting input Tn through the PNP transistors Tr52 and Tr54, it produces a signal as a function of a difference between currents (i.e., a potential difference) flowing through the transistors Tr52 and Tr54. The control circuit 70 amplifies the signal inputted from the differential amplifier 50 to activate the pair of the output transistors Tr61 and Tr62 of the output circuit 60 simultaneously.
Specifically, the signal is outputted from the output terminal To as a function of the potential difference between the signals inputted to the non-inverting input Tp and the inverting input Tn. The phase-compensating capacitor C71 disposed between a path for the output transistor-driving signal extending from the control circuit 70 to the output circuit 60 and a path of the current-amplifying circuit on the side of the non-inverting input Tp serves to avoid oscillation of the operational amplifier.
The differential amplifier 50 of the above described operational amplifier produces a signal as a function of the potential difference between the input signals to the non-inverting input Tp and the inverting input Tn to drive the output transistors Tr61 and Tr62 simultaneously. Specifically, a drive system for the output transistors Tr61 and Tr62 in the control circuit 70 is made of a single line. The output circuit 60 is made of the so-called push-pull circuit in which the output transistor Tr61 on the positive voltage side is implemented by an NPN transistor, and the output transistor Tr62 on the negative voltage side is implemented by a PNP transistor. The operational amplifier, thus, needs to install the NPN transistor Tr73 between the base of each of the output transistors Tr61 and Tr62 connected together and the ground line Lg and control the base voltage of each of the output transistor Tr61 and Tr62 (i.e., the output voltage from the output terminal To). This causes a minimum output voltage from the output terminal To to be, as indicated by a solid line in FIG. 5(b), a voltage (Vce+Vf=approximately 0.8V) that is higher than the voltage of the ground line Lg (i.e., ground potential) by the sum of the collector-emitter voltage Vce (approximately 0.1V) of the NPN transistor Tr73 and the emitter-base forward voltage Veb (the so-called Vf=approximately 0.7V) of the output transistor Tr62.
In order to control the base voltage of each of the output transistors Tr61 and Tr62, the constant current is supplied from the PNP transistor Tr71 to the drive line for each of the output transistors Tr61 and Tr62. The PNP transistor Tr71 is disposed between the base of the output transistor Tr61 and the power supply line Lv. This causes a maximum output voltage from the output terminal To to be, as indicated by the solid line in FIG. 5(b), a voltage (Vccxe2x88x92(Vce+Vf)) that is lower than the voltage of the power supply line Lv (i.e., the source voltage Vcc=approximately 0.1V) by the sum of the collector-emitter voltage Vce (approximately 0.1V) of the NPN transistor Tr71 and the emitter-base forward voltage Veb (i.e., Vf=approximately 0.7V) of the output transistor Tr61.
Note that FIG. 5(b) represents a change in output voltage Vout from the output terminal To when the input voltage Vin to a non-inverting input of an operational amplifier, as shown in FIG. 5(a), which connects at an output thereof with an inverting input thereof to define the so-called voltage follower is changed from 0V to the source voltage Vcc.
As apparent from the above, an output voltage range (i.e., a dynamic range) over which the voltage is outputted from the output terminal To is between (Vbe+Vce) and (Vccxe2x88x92(Vbe+Vce)), thus requiring the dynamic range of the operational amplifier to be increased further.
In recent years, semiconductor devices tend to be made of an LSI for the multiplicity of functions. An increase in operational speed and a reduction in size are required. These requirements, however, result in an increase in power consumption and difficulty in dissipating the heat from the semiconductor devices. Further, the semiconductor devices are also required to be operated by a portable battery. To decrease the power consumption and operate the semiconductor devices by the portable battery, the source voltage required by the semiconductor devices needs to be lowered.
The operational amplifier used as one component of the semiconductor device, however, encounters the drawback in that the lowering of the source voltage results in a decrease in voltage range of the output signal, thus causing an S/N ratio to deteriorate. Particularly, in the above operational amplifier not using a negative power supply, a minimum output voltage is, as described above, higher than the ground voltage of the dc power supply by approximately 0.8V (=Vbe+Vce), while a maximum output voltage is lower than the source voltage by approximately 0.8V (=Vbe+Vce). Thus, if the source voltage Vcc of the dc power supply is lowered from a typical voltage 5V to 3V, for example, it will cause an available output voltage range to be narrowed greatly to 0.8V to 2.2V, encountering a difficulty in ensuring the quality of an output signal. For this reason, the output voltage range of the operational amplifier delimited as a function of the source voltage has been required to be increased.
In order to increase the output voltage range (i.e., the dynamic range) of the operational amplifier, there has been proposed a circuit structure, as shown in FIG. 5(c), in which the voltage higher than the source voltage Vcc by approximately 1V is applied to an output transistor (NPN transistor) on a positive voltage side of a push-pull circuit working as an output stage of the operational amplifier, and the voltage lower than the ground voltage by approximately 1V is applied to an output transistor (PNP transistor) on a negative voltage side, thereby increasing the output voltage range from approximately 0V up to the source voltage Vcc. This structure, however, requires a voltage converter made by a step-up circuit for producing the voltage to be applied to the push-pull circuit. The formation of such a voltage converter in an IC constituting the operational amplifier will cause switching noises to arise upon voltage conversion as well as an increase in manufacturing cost and also requires the operational amplifier to be designed to withstand higher voltages. It, thus, becomes necessary to modify the design of the IC greatly. An IC of this type are, as the case my be, not available.
It is therefore a principal object of the invention to avoid the disadvantages of the prior art.
It is another object of the invention to provide an operational amplifier which is designed to have an increased output voltage range without applying a stepped up source voltage to output transistors.
According to one aspect of the invention, there is provided an operational amplifier which comprises: (a) a differential amplifier including a first input transistor connected to an inverting input and a second input transistor connected to a non-inverting input, the differential amplifier being responsive to the input signal to the inverting input to establish a current flow through the first input transistor to provide a first signal and responsive to the input signal to the non-inverting input to establish a current flow through the second input transistor to provide a second signal; (b) an output circuit including a first output transistor which is disposed in a current line extending from a positive voltage side of a dc power supply to an output terminal of the operational amplifier and which connects at a first terminal with the positive voltage side of the dc power supply and at a second terminal with the output terminal and a second output transistor which is disposed in a current line extending from a negative voltage side of the dc power supply to the output terminal and which connects at a first terminal with the output terminal and at a second terminal with the negative voltage side of the dc power supply; (c) a control circuit supplied with a power from the dc power supply to control the output circuit, the control circuit working to produce a first drive signal to develop a drive voltage across the second terminal and a control terminal of the first output transistor in response to the first signal inputted from the differential amplifier and to produce a second drive signal to develop a drive voltage across the second terminal and a control terminal of the second output transistor in response to the second signal inputted from the differential amplifier so as to output a signal from the output terminal as a function of the potential difference between the input signals to the inverting input and the non-inverting input, the control circuit including a first control circuit designed to be responsive to the first signal outputted from the differential amplifier to control the first drive signal so as to decrease a current flowing through the first output transistor as a potential of the input signal to the inverting input rises and a second control circuit designed to be responsive to the second signal outputted from the differential amplifier to control the second drive signal so as to decrease a current flowing through the second output transistor as a potential of the input signal to the non-inverting input rises; and (d) phase-compensating capacitors disposed between the output terminal of the operational amplifier and a portion of the first control circuit leading to the control terminal of the first output transistor and between the output terminal of the operational amplifier and a portion of the second control circuit leading to the control terminal of the second output transistor.
In the preferred mode of the invention, the first output transistor is implemented by an NPN transistor which has a collector connected to the positive voltage side of the dc power supply as the first terminal, an emitter connected to the output terminal of the operational amplifier as the second terminal, and a base working as the control terminal into which the first drive signal is inputted. The second output transistor is implemented by an NPN transistor which has a collector connected to the output terminal of the operational amplifier as the first terminal, an emitter connected to the negative voltage side of the dc power supply as the second terminal, and a base working as the control terminal into which the second drive signal is inputted.
The differential amplifier includes a first differential amplifier circuit having disposed therein the first and second input transistors and a second differential amplifier circuit having a first and a second transistor which are connected to the first and second input transistors, respectively, and which produce the first and second signals as functions of currents flowing through the first and second transistors, respectively.
The inverting input is coupled to the output terminal to form the operational amplifier as a voltage follower which supplies a power to an external device connected to the output terminal as a function of the input signal to the non-inverting input.
According to the second aspect of the invention, there is provided an operational amplifier which comprises: (a) a differential amplifier including a first input transistor connected to an inverting input and a second input transistor connected to a non-inverting input, the differential amplifier being responsive to the input signal to the inverting input to establish a current flow through the first input transistor to provide a first signal and responsive to the input signal to the non-inverting input to establish a current flow through the second input transistor to provide a second signal; (b) an output circuit including a first output transistor which is disposed in a current line extending from a positive voltage side of a dc power supply to an output terminal of the operational amplifier and which connects at a first terminal with the positive voltage side of the dc power supply and at a second terminal with the output terminal and a second output transistor which is disposed in a current line extending from a negative voltage side of the dc power supply to the output terminal and which connects at a first terminal with the output terminal and at a second terminal with the negative voltage side of the dc power supply; (c) a control circuit supplied with a power from the dc power supply to control the output circuit, the control circuit working to produce a first drive signal to develop a drive voltage across the first terminal and a control terminal of the first output transistor in response to the first signal inputted from the differential amplifier and to produce a second drive signal to develop a drive voltage across the second terminal and a control terminal of the second output transistor in response to the second signal inputted from the differential amplifier so as to output a signal from the output terminal as a function of the potential difference between the input signals to the inverting input and the non-inverting input, the control circuit including a first control circuit designed to be responsive to the first signal outputted from the differential amplifier to control the first drive signal so as to decrease a current flowing through the first output transistor as a potential of the input signal to the inverting input rises and a second control circuit designed to be responsive to the second signal outputted from the differential amplifier to control the second drive signal so as to decrease a current flowing through the second output transistor as a potential of the input signal to the non-inverting input rises; and (d) phase-compensating capacitors disposed between the output terminal of the operational amplifier and a portion of the first control circuit leading to the control terminal of the first output transistor and between the output terminal of the operational amplifier and a portion of the second control circuit leading to the control terminal of the second output transistor.
In the preferred mode of the invention, the first output transistor is implemented by a PNP transistor which has an emitter connected to the positive voltage side of the dc power supply as the first terminal, a collector connected to the output terminal of the operational amplifier as the second terminal, and a base working as the control terminal into which the first drive signal is inputted. The second output transistor is implemented by an NPN transistor which has a collector connected to the output terminal of the operational amplifier as the first terminal, an emitter connected to the negative voltage side of the dc power supply as the second terminal, and a base working as the control terminal into which the second drive signal is inputted.
The differential amplifier includes a first differential amplifier circuit having disposed therein the first and second input transistors and a second differential amplifier circuit having a first and a second transistor which are connected to the first and second input transistors, respectively, and which produce the first and second signals as functions of currents flowing through the first and second transistors, respectively.
The inverting input is coupled to the output terminal to form the operational amplifier as a voltage follower which supplies a power to an external device connected to the output terminal as a function of the input signal to the non-inverting input.
According to the third aspect of the invention, there is provided an operational amplifier which comprises: (a) a differential amplifier producing an output signal as a function of a potential difference between an input signal to an inverting input and an input signal to a non-inverting input; (b) an output circuit including a first output transistor which is disposed in a circuit line extending from a positive voltage side of a dc power supply to an output terminal of the operational amplifier and a second output transistor which is disposed in a circuit line extending from a negative voltage side of the dc power supply to the output terminal; and (c) a control circuit controlling the output circuit, the control circuit working to produce a first drive signal and a second drive signal having different levels as a function of the output signal from the differential amplifier, the first drive signal working to activate the first output transistor as a function of the level of the first drive signal to establish a connection between the output terminal and the positive voltage side of the dc power supply through the first output transistor, the second drive signal working to activate the second output transistor as a function of the level of the second drive signal to establish a connection between the output terminal and the negative voltage side of the dc power supply through the second output transistor, thereby outputting a signal from the output terminal as a function of the potential difference between the input signals to the inverting input and the non-inverting input.
In the preferred mode of the invention, when the input signal to the non-inverting input is at a higher level substantially equal to a potential of the positive voltage side of the dc power supply, and the input signal to the inverting input is at a lower level substantially equal to a potential of the negative voltage side of the dc power supply, the first drive signal activates the first output transistor to establish the connection between the output terminal and the positive voltage side of the dc power supply, and the second drive signal deactivates the second output transistor to block the connection between the output terminal and the negative voltage side of the dc power supply. When the input signal to the non-inverting input is at the lower level, and the input signal to the inverting input is at the higher level, the first drive signal deactivates the first output transistor to block the connection between the output terminal and the positive voltage side of the dc power supply, and the second drive signal activates the second output transistor to establish the connection between the output terminal and the negative voltage side of the dc power supply.
The first output transistor is implemented by a bipolar transistor which connects at a collector with the output terminal, at an emitter with the positive voltage side of the dc power supply, and at a base with the control circuit. The second output transistor is implemented by a bipolar transistor which connects at a collector with the output terminal, at an emitter with the negative voltage side of the dc power supply, and at a base with the control circuit.
The first output transistor is implemented by a MOSEFT which connects at a drain with the output terminal, at a source with the positive voltage side of the dc power supply, and at a gate with the control circuit. The second output transistor is implemented by a MOSFET which connects at a drain with the output terminal, at a source with the negative voltage side of the dc power supply, and a gate with the control circuit.